The present invention relates generally to semiconductor memory devices, and, more particularly, to a word line driver circuit for a semiconductor memory device which utilizes a low voltage power supply.
In recent years, the demand for battery-powered portable computers has increased rapidly. However, in order to maximize the utility of such battery-powered portable computers, and thus satisfy the needs of users of such battery-powered portable computers, it is becoming increasingly necessary to maximize the time that such computers can be used before it becomes necessary to recharge the battery. In this connection, it is widely recognized that the amount of battery power consumed by the semiconductor memory devices utilized in such portable computers is a major factor in achieving the goal of maximizing the use time of such portable computers between required battery recharges. Therefore, there is an increasing demand for semiconductor memory devices which utilize increasingly lower voltage power supplies, and which consume increasingly less power, to thereby minimize the drain of battery power due to the power consumption of the semiconductor memory devices utilized in portable computers.
In high capacity semiconductor memory devices, such as dynamic random access memories (DRAMs), which utilize a low voltage power supply, it has been necessary to utilize word line driver circuits which internally boost the power supply voltage for driving the word lines thereof above that of the low voltage power supply, in order to ensure accurate and reliable operation thereof. Such a word line driver circuit is described in IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, November 1991, pg. 1557. This conventional word line driver circuit is depicted in FIG. 1.
With reference now to FIG. 1, the operation of the conventional word line driver circuit depicted therein will now be described. More particularly, a row decoding signal X.sub.D generated by a row decoder (not shown) is applied, through an NMOS transfer transistor M1, to the gate of a pull-up NMOS transistor M2. The gate of the transfer transistor M1 is coupled to a power supply voltage Vcc. When the row decoding signal X.sub.D is high, the pull-up transistor M2 is turned on, and pull-down NMOS transistor M3 is turned off by the inverted row decoding signal X.sub.D, thereby transferring the word line drive signal .phi.XI to a word line WL of the semiconductor memory device.
The word line drive signal .phi.XI is generated by an internal boosting circuit (not shown) of the semiconductor memory device, and has a voltage level of Vcc+VTN, where VTN is the threshold voltage of an NMOS transistor. Gate node N1 intermediate the gate electrode of the pull-up transistor M2 and the channel of the transfer transistor M1 is precharged to a voltage level of Vcc-VTN when the row decoding signal X.sub.D is activated, due to the voltage drop (VTN) across the transfer transistor M1. The pull-up transistor M2 is turned on by the precharge voltage Vcc-VTN, and the word line drive signal .phi.XI is transferred to the word line WL via the channel of the turned-on pull-up transistor M2.
Due to the gate capacitance of the pull-up transistor M2, a self-boosting phenomenon occurs which enables the word line drive signal .phi.XI to pass through the channel of the pull-up transistor M2 without any voltage drop, so that the full voltage level Vcc+VTN of the word line drive signal .phi.XI is applied to the word line WL.
However, the above-described conventional word line drive circuit still suffers from the following drawbacks and shortcomings. Namely, because the voltage applied to the gate of the pull-up transistor M2 is only Vcc-VTN, there is an unwanted delay in transferring the full voltage level Vcc+VTN of the word line drive signal .phi.XI to the word line WL. Further, if the power supply voltage Vcc drops (e.g., due to fluctuations of Vcc), the full boosted word line drive signal .phi.XI is not transferred to the word line WL.
Based on the above, it can be appreciated that there presently exists a need in the art for a word line drive circuit which overcomes the above-described disadvantages and shortcomings of the presently available word line drive circuits. The present invention fulfills this need.